2 ms·
No, the QSPI device is simply memory mapped as in quite a lot (most) microcontrollers. The external QSPI FLASH just appears in the normal memory map, no demand
by TickleSteve 10y ago
No, the QSPI device is simply memory mapped as in quite a lot (most) microcontrollers.
The external QSPI FLASH just appears in the normal memory map, no demand-paging.
Normally used for eXecute-In-Place code (XIP) when the code is too large for the internal FLASH.
There is a performance trade-off, and external QSPI FLASH might run its bus at (for example) 50MHz, but thats still much slower than internal FLASH directly attached to the bus.
- david-given 10y agoBut SPI devices can't be memory mapped --- it's a serial protocol and they can't be attached to the bus. For this to work, something must be converting bus accesses into SPI requests. And then, at least assuming it's not doing an SPI read for every access, it needs to cache the result somewhere... but you've just said it's not doing demand paging? I am now really confused.
- makomk 10y agoIt's got a standard two-way associative cache in front of the SPI interface, much like you might have between RAM and the external bus in a normal CPU. If availabkle, demand paging would be the next step after the data wasn't found there either - a slower, higher-level concept that's handled in software rather than hardware.
- TickleSteve 10y agoThere is a hardware block within the processor that converts memory-bus accesses into SPI accesses (for devices supporting the SPIFI standard for example). This makes the whole SPI device appear to be memory-mapped (for read accesses).