3 ms·
The RISC-V seems to have it's focus on being open and being simple, not so much on being the fastest. The specs are only 130 pages. https://riscv.org/risc-v-fo
by iammyIP 10y ago
The RISC-V seems to have it's focus on being open and being simple, not so much on being the fastest. The specs are only 130 pages.
https://riscv.org/risc-v-foundation/ https://riscv.org/risc-v-foundation/
https://riscv.org/specifications/ https://riscv.org/specifications/
- monocasa 10y agoIt's a simple ISA, but built to be fast. It's specifically designed to map well to OoO cores at the slight expense of some features on in order cores that give you little boosts (like branch delay slots and other exposed pipeline features). Last I saw, BOOM compared very well to other OoO cores at the same gate count.
- userbinator 10y agoIf anything I think RISC-V is repeating the same mistakes as MIPS and the original RISCs, by being far too simple and requiring much greater fetch bandwidth in the process. The performance of MIPS, which it is closest to, has never really been considered anything more than "acceptable". It loses to ARM (which isn't so RISC-y anyway) and x86, so I expect RISC-V to be about the same: https://www.extremetech.com/extreme/188396-the-final-isa-showdown-is-arm-x86-or-mips-intrinsically-more-power-efficient https://www.extremetech.com/extreme/188396-the-final-isa-sho... http://www.extremetech.com/wp-content/uploads/2014/08/AverageEnergy.png http://www.extremetech.com/wp-content/uploads/2014/08/Averag... Compared to an 8-bit AVR in an Arduino it's definitely much faster, but compared to other 32-bit architectures, it is not.