This is great! The source code is written in Verilog HDL and is located here[0]. I hope they use english instead of spanish as a language to attract more contri

This is great! The source code is written in Verilog HDL and is located here[0]. I hope they use english instead of spanish as a language to attract more contributors. [0] - https://github.com/onchipuis/mriscvcore https://github.com/onchipuis/mriscvcore