You can estimate to some extent based on FPGA resources. For example you know you need X thousand flip-flops, Y hundred block RAMs, and Z hundred DSP blocks. An

You can estimate to some extent based on FPGA resources. For example you know you need X thousand flip-flops, Y hundred block RAMs, and Z hundred DSP blocks. And then you look at the switching speed specs and guess how fast you can clock it. But in the projects that I've been involved with, it turns out that it just wasn't feasible to route all the stuff that was originally envisioned at the planned speed. Interconnect is a big killer of hopes and dreams, once your FPGA starts to fill up. Really, the only way to be sure is to run your design all the way from synthesis to place and route. The problem with that is you rarely have the luxury of starting a hardware design with all the HDL already written.