3 ms·

I'm putting money on something to do with ZFS. Turns out bit flips are significantly more common than had been thought in the past, which makes a error-correcti

I'm putting money on something to do with ZFS. Turns out bit flips are significantly more common than had been thought in the past, which makes a error-correcting file system somewhat risky to use with normal non-ecc ram.

Someone 10y ago
But if you use ZFS, chances are you will want to have lots of disk space and lots of disks, too. If so, why buy a small box?
- Declanomous 10y ago
  Because you are paranoid and also have a small apartment. I have a mini-itx home server build with 16 gb of ram and 4 WD 3tb RED drives. It doesn't run ZFS because I don't have ECC ram in it, but it's the smallest computer I could buy that would fit the hard disks I already owned. If I were starting from scratch I'd probably use 2.5" drives instead, and if I wasn't working for a non-profit, I'd probably use SSDs now that they are about $.27 a gb.
  - Someone 10y ago
    Mini-itx I can understand, but this box has one drive of 1.5TB max (according to http://www.hp.com/go/Z2mini http://www.hp.com/go/Z2mini). You would have to connect any other drives externally. If you do that, the result probably takes more room than that mini-itx.
  - Tomte 10y ago
    ZFS isn't worse than other file systems without ECC RAM. It's just that it's much better with ECC RAM.
Tomte 10y ago
In the safety industry everyone knows that bit flips (SEUs) are way more common than laypeople believe. And that's for embedded microcontrollers and RAM that aren't nearly pushing it to extremely small processes. Let me just quote IEC 61508, where "FIT" means 10e-9 h: Causes of soft errors are: (1) Alpha particles from package decay, (2) Neutrons, (3) external EMI noise, (4) Internal cross-talk. External EMI noise is covered by other requirements of this international standard. A soft error occurs when a radiation event causes enough of a charge disturbance to reverse or flip the data state of a low energized semiconductor memory cell, register, latch, or flip-flop. The error is called “soft” because the circuit itself is not permanently damaged by the radiation. Soft-errors are classified in Single Bit Upsets (SBU) or Single Event Upsets (SEU) and Multi-Bit Upsets (MBU). The soft error rate has been reported (see a) and i) below) to be in a range of 700 Fit/MBit to 1 200 Fit/MBit for (embedded) memories. This is a reference value to be compared with data coming from the silicon process with which the device is implemented. Until recently SBU were considered to be dominant, but the latest forecast (see a) below) reports a growing percentage of MBU of the overall soft-error rate (SER) for technologies from 65 nm down. The following literature and sources give details about soft-errors: a) Altitude SEE Test European Platform (ASTEP) and First Results in CMOS 130 nm SRAM. J-L. Autran, P. Roche, C. Sudre et al. Nuclear Science, IEEE Transactions on Volume 54, Issue 4, Aug. 2007 Page(s):1002 - 1009 b) Radiation-Induced Soft Errors in Advanced Semiconductor Technologies, Robert C. Baumann, Fellow, IEEE, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005 c) Soft errors' impact on system reliability, Ritesh Mastipuram and Edwin C Wee, Cypress Semiconductor, 2004 d) Trends And Challenges In VLSI Circuit Reliability, C. Costantinescu, Intel, 2003, IEEE Computer Society e) Basic mechanisms and modeling of single-event upset in digital microelectronics, P. E. Dodd and L. W. Massengill, IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 583–602, Jun. 2003. f) Destructive single-event effects in semiconductor devices and ICs, F. W. Sexton, IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 603–621, Jun. 2003. g) Coming Challenges in Microarchitecture and Architecture, Ronen, Mendelson, Proceedings of the IEEE, Volume 89, Issue 3, Mar 2001 Page(s):325 – 340 h) Scaling and Technology Issues for Soft Error Rates, A Johnston, 4th Annual Research Conference on Reliability Stanford University, October 2000 i) International Technology Roadmap for Semiconductors (ITRS), several papers.
- pYQAJ6Zm 10y ago
  So, for let’s say 1 TB, if my calculations follow this correctly, that would be between ~6 and ~10 SEU/h. I am worried about my personal backups now.
  - Tomte 10y ago
    This is for (S)RAM. I don't know the event rates for flash off the top of my head, but I'd expect them to be at least an order of magnitude lower. But take 16GB. With 1000 FIT you get pretty much \pi events in one day.

Someone 10y ago

But if you use ZFS, chances are you will want to have lots of disk space and lots of disks, too. If so, why buy a small box?

Declanomous 10y ago
Because you are paranoid and also have a small apartment. I have a mini-itx home server build with 16 gb of ram and 4 WD 3tb RED drives. It doesn't run ZFS because I don't have ECC ram in it, but it's the smallest computer I could buy that would fit the hard disks I already owned. If I were starting from scratch I'd probably use 2.5" drives instead, and if I wasn't working for a non-profit, I'd probably use SSDs now that they are about $.27 a gb.
- Someone 10y ago
  Mini-itx I can understand, but this box has one drive of 1.5TB max (according to http://www.hp.com/go/Z2mini http://www.hp.com/go/Z2mini). You would have to connect any other drives externally. If you do that, the result probably takes more room than that mini-itx.
- Tomte 10y ago
  ZFS isn't worse than other file systems without ECC RAM. It's just that it's much better with ECC RAM.

Tomte 10y ago

In the safety industry everyone knows that bit flips (SEUs) are way more common than laypeople believe. And that's for embedded microcontrollers and RAM that aren't nearly pushing it to extremely small processes. Let me just quote IEC 61508, where "FIT" means 10e-9 h: Causes of soft errors are: (1) Alpha particles from package decay, (2) Neutrons, (3) external EMI noise, (4) Internal cross-talk. External EMI noise is covered by other requirements of this international standard. A soft error occurs when a radiation event causes enough of a charge disturbance to reverse or flip the data state of a low energized semiconductor memory cell, register, latch, or flip-flop. The error is called “soft” because the circuit itself is not permanently damaged by the radiation. Soft-errors are classified in Single Bit Upsets (SBU) or Single Event Upsets (SEU) and Multi-Bit Upsets (MBU). The soft error rate has been reported (see a) and i) below) to be in a range of 700 Fit/MBit to 1 200 Fit/MBit for (embedded) memories. This is a reference value to be compared with data coming from the silicon process with which the device is implemented. Until recently SBU were considered to be dominant, but the latest forecast (see a) below) reports a growing percentage of MBU of the overall soft-error rate (SER) for technologies from 65 nm down. The following literature and sources give details about soft-errors: a) Altitude SEE Test European Platform (ASTEP) and First Results in CMOS 130 nm SRAM. J-L. Autran, P. Roche, C. Sudre et al. Nuclear Science, IEEE Transactions on Volume 54, Issue 4, Aug. 2007 Page(s):1002 - 1009 b) Radiation-Induced Soft Errors in Advanced Semiconductor Technologies, Robert C. Baumann, Fellow, IEEE, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 5, NO. 3, SEPTEMBER 2005 c) Soft errors' impact on system reliability, Ritesh Mastipuram and Edwin C Wee, Cypress Semiconductor, 2004 d) Trends And Challenges In VLSI Circuit Reliability, C. Costantinescu, Intel, 2003, IEEE Computer Society e) Basic mechanisms and modeling of single-event upset in digital microelectronics, P. E. Dodd and L. W. Massengill, IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 583–602, Jun. 2003. f) Destructive single-event effects in semiconductor devices and ICs, F. W. Sexton, IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 603–621, Jun. 2003. g) Coming Challenges in Microarchitecture and Architecture, Ronen, Mendelson, Proceedings of the IEEE, Volume 89, Issue 3, Mar 2001 Page(s):325 – 340 h) Scaling and Technology Issues for Soft Error Rates, A Johnston, 4th Annual Research Conference on Reliability Stanford University, October 2000 i) International Technology Roadmap for Semiconductors (ITRS), several papers.

pYQAJ6Zm 10y ago
So, for let’s say 1 TB, if my calculations follow this correctly, that would be between ~6 and ~10 SEU/h. I am worried about my personal backups now.
- Tomte 10y ago
  This is for (S)RAM. I don't know the event rates for flash off the top of my head, but I'd expect them to be at least an order of magnitude lower. But take 16GB. With 1000 FIT you get pretty much \pi events in one day.