I was thinking more in terms of realizing signals are actual electrical nodes, not location in memory, separating the design in combinations and sequential part

I was thinking more in terms of realizing signals are actual electrical nodes, not location in memory, separating the design in combinations and sequential parts and choosing the right size of buffer going from one clock domain to another and stuff like that. When I see examples of verilog online, it seems like most people have no concept of these core things