I think it is true that the less experienced engineers start in verification however the verification role is actually quite difficult. It is much more than fee

I think it is true that the less experienced engineers start in verification however the verification role is actually quite difficult. It is much more than feeding tools and math. You only do that during the execution phase. That can be assigned to newbies. However the creation of the verification testbench and tests is as extensive as the design. The verification team has to work in parallel with the design team so they have enough time to get things done. If they make a mistake in verification it can still also cost a fortune. If the testbench and tests are not well designed then you are screwed in a roundabout way because the ability to quickly find the bugs isn't there. The testbench has to work on both the rtl and the back annotated netlist. Approximately 75% of the person-months and compute resources for most projects is verification work. I have been verification lead on multiple projects and design lead on multiple projects. In either role I always looked to assign verification resources as top priority because the project is screwed without it. On the original topic: The problem is that most commenters are not in the verification field. They don't know the amount or type of work done in verification or the commercial tools involved. This is done in SystemVerilog to do UVM - Universal Verification Methodology. It is not just Verilog. People here are concerned with ease of design. The bottleneck in the industry is in ease of verification.