4 ms·
>> I wonder if Verilog is even appropriate for what you're talking about, except for legacy reasons. Doing some work with HDL in a university research setting
by blackguardx 10y ago
>> I wonder if Verilog is even appropriate for what you're talking about, except for legacy reasons.
Doing some work with HDL in a university research setting is different than shipping a working product with the associated constraints.
- aninhumer 10y agoSure, my point is that Verilog (and RTL in general) doesn't seem any more appropriate for expressing the kind of designs you're talking about than a more abstract HDL would be. The only reason I'd even think about using it is if there weren't any alternative tools which could express layout (which is unfortunately probably the case, and exactly why you are using it).