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Sure, we were doing processor architecture research, and our focus was whether new features improved software performance (while maintaining timing, and not usi
by aninhumer 10y ago
Sure, we were doing processor architecture research, and our focus was whether new features improved software performance (while maintaining timing, and not using too much extra area), and how they could work alongside complicated processor designs. Our challenges were mostly about ensuring correct behaviour rather than meeting tight performance requirements.
Obviously these are very different fields, to the extent that I wonder if Verilog is even appropriate for what you're talking about, except for legacy reasons. If you're working in a domain where layout is so important, it feels like you should be using a tool that represents it directly, rather than inferring it.
- blackguardx 10y ago>> I wonder if Verilog is even appropriate for what you're talking about, except for legacy reasons. Doing some work with HDL in a university research setting is different than shipping a working product with the associated constraints.
- aninhumer 10y agoSure, my point is that Verilog (and RTL in general) doesn't seem any more appropriate for expressing the kind of designs you're talking about than a more abstract HDL would be. The only reason I'd even think about using it is if there weren't any alternative tools which could express layout (which is unfortunately probably the case, and exactly why you are using it).