I had a pretty cool class project once where we built the same formula solver in Verilog using three different optimizations: latency, power (watts), and area (

I had a pretty cool class project once where we built the same formula solver in Verilog using three different optimizations: latency, power (watts), and area (in terms of PLU usage). I spent a long time just diagramming the timing of the various fp arithmetic blocks before I even touched the keyboard. Each design had its own quirks I had to factor in. Each block has a slightly different propagation latency so getting everything to pipeline synchronously with shift registers was certainly a chore.