Chisel has a lower level model, but since it's Scala, it's a much higher level language than SystemC or SystemVerilog. Sure you have to specify things at the g

Chisel has a lower level model, but since it's Scala, it's a much higher level language than SystemC or SystemVerilog. Sure you have to specify things at the gate level, but you have the power to build abstractions on top of that (and indeed most of the ones other HDLs would provide are already there).