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>Verilog seems "hard" because people often use it in a similar fashion to a programming language You mean typing random stuff into the editor without understan
by romaniv 10y ago
>Verilog seems "hard" because people often use it in a similar fashion to a programming language
You mean typing random stuff into the editor without understanding what any of it does and hoping for the best? Because all of the online examples I've seen of "HDL done like programming" involved exactly that. In my experience, HDL design is very similar to functional programming (minus recursion) and the principles that work in one translate well to the other.
- tonmoy 10y agoI was thinking more in terms of realizing signals are actual electrical nodes, not location in memory, separating the design in combinations and sequential parts and choosing the right size of buffer going from one clock domain to another and stuff like that. When I see examples of verilog online, it seems like most people have no concept of these core things