4 ms·

Sure locality is important, but I think you're overestimating the necessity of planning for it. When I was doing hardware design a few years ago, I wasn't worry

Sure locality is important, but I think you're overestimating the necessity of planning for it. When I was doing hardware design a few years ago, I wasn't worrying about the physical layout of anything. We kept the interconnect limited to a modular hierarchy, and we didn't seem to have many problems. Of course, we were in a research group, so performance was less important to us. And we were working with FPGAs, so we didn't need to get it right in one go (and I think the fabric is better able to cope with looser style). That said, I think there are cases where you can afford to sacrifice a bit of design efficiency to increase development speed. And if you're working with FPGAs, you may even be able to optimise later. EDIT: Also the impression I got is that while industry does spend a lot of effort on it, complex designs are nowhere near as optimal as they could be. The first clue should be that an Intel chip has clearly defined blocks on it, rather than being a mess of interleaved logic. They divide the design like that to make it tractable for the designers. > If you did the equivalent in silicon (like move the location of a group of transistors), at best it would break your functionality and at worst it would make the design unsynthesizable. I don't think this makes much sense unless you're presupposing a prescriptive physical layout. Sure, if you were to move a bunch of synthesized circuitry somewhere else and then try to reconnect it, it's not going to work. But that's not something you'd actually do in an abstract model. What you might do is move a bunch of HDL logic from somewhere in the module hierarchy to somewhere else, in which case the synthesizer will move everything else around to compensate.

akiselev 10y ago
>> Of course, we were in a research group, so performance was less important to us. And we were working with FPGAs, so we didn't need to get it right in one go. What were you researching/designing? The higher your clock speeds/bandwidth requirements are and the more complex your designs, the more locality matters. The last design I worked on, for example, was a 32x32 crosspoint switch with total bandwidth in the low hundreds of gigabits and we eventually had to tweak cell locations manually on the mask to get the design working to spec. In modern chip design, bandwidth on that scale is pretty common so i don't think we're talking about the extremes of hardware design. >> I don't think this makes much sense unless you're presupposing a prescriptive physical layout. Sure, if you were to move a bunch of synthesized circuitry somewhere else and then try to reconnect it, it's not going to work. But that's not something you'd actually do in an abstract model. Again, depends on a variety of factors. Some of the designs I've worked on have had internal clock signals that couldn't travel across a fraction of the chip before attenuating too much to switch a transistor. Sure a low speed design can be synthesized without caring about physical layout but once you're in the RF/high speed digital realm, the relative location of dependent high speed blocks matters much more and the HDL abstractions start to leak or breakdown entirely.
- aninhumer 10y ago
  Sure, we were doing processor architecture research, and our focus was whether new features improved software performance (while maintaining timing, and not using too much extra area), and how they could work alongside complicated processor designs. Our challenges were mostly about ensuring correct behaviour rather than meeting tight performance requirements. Obviously these are very different fields, to the extent that I wonder if Verilog is even appropriate for what you're talking about, except for legacy reasons. If you're working in a domain where layout is so important, it feels like you should be using a tool that represents it directly, rather than inferring it.
  - blackguardx 10y ago
    >> I wonder if Verilog is even appropriate for what you're talking about, except for legacy reasons. Doing some work with HDL in a university research setting is different than shipping a working product with the associated constraints.
    - aninhumer 10y ago
      Sure, my point is that Verilog (and RTL in general) doesn't seem any more appropriate for expressing the kind of designs you're talking about than a more abstract HDL would be. The only reason I'd even think about using it is if there weren't any alternative tools which could express layout (which is unfortunately probably the case, and exactly why you are using it).
tonmoy 10y ago
About the chips not being "optimal", say an Intel processor has 50M gates, to be placed in a 50M squares (all possible layouts). Then there would be factorial(50M) possibilities. If you could simulate each one every clock cycle, you would need 10^1000000000 seconds. The age of the universe is about 10^17 seconds. It is just not practical to omptimize the layout like that. And having all gates in blocks gets us very acceptable local optima anyways (gates inside a block tend to be more interconnected with each other most of the cases) EDIT: clarification

akiselev 10y ago

>> Of course, we were in a research group, so performance was less important to us. And we were working with FPGAs, so we didn't need to get it right in one go. What were you researching/designing? The higher your clock speeds/bandwidth requirements are and the more complex your designs, the more locality matters. The last design I worked on, for example, was a 32x32 crosspoint switch with total bandwidth in the low hundreds of gigabits and we eventually had to tweak cell locations manually on the mask to get the design working to spec. In modern chip design, bandwidth on that scale is pretty common so i don't think we're talking about the extremes of hardware design. >> I don't think this makes much sense unless you're presupposing a prescriptive physical layout. Sure, if you were to move a bunch of synthesized circuitry somewhere else and then try to reconnect it, it's not going to work. But that's not something you'd actually do in an abstract model. Again, depends on a variety of factors. Some of the designs I've worked on have had internal clock signals that couldn't travel across a fraction of the chip before attenuating too much to switch a transistor. Sure a low speed design can be synthesized without caring about physical layout but once you're in the RF/high speed digital realm, the relative location of dependent high speed blocks matters much more and the HDL abstractions start to leak or breakdown entirely.

aninhumer 10y ago
Sure, we were doing processor architecture research, and our focus was whether new features improved software performance (while maintaining timing, and not using too much extra area), and how they could work alongside complicated processor designs. Our challenges were mostly about ensuring correct behaviour rather than meeting tight performance requirements. Obviously these are very different fields, to the extent that I wonder if Verilog is even appropriate for what you're talking about, except for legacy reasons. If you're working in a domain where layout is so important, it feels like you should be using a tool that represents it directly, rather than inferring it.
- blackguardx 10y ago
  >> I wonder if Verilog is even appropriate for what you're talking about, except for legacy reasons. Doing some work with HDL in a university research setting is different than shipping a working product with the associated constraints.
  - aninhumer 10y ago
    Sure, my point is that Verilog (and RTL in general) doesn't seem any more appropriate for expressing the kind of designs you're talking about than a more abstract HDL would be. The only reason I'd even think about using it is if there weren't any alternative tools which could express layout (which is unfortunately probably the case, and exactly why you are using it).

tonmoy 10y ago

About the chips not being "optimal", say an Intel processor has 50M gates, to be placed in a 50M squares (all possible layouts). Then there would be factorial(50M) possibilities. If you could simulate each one every clock cycle, you would need 10^1000000000 seconds. The age of the universe is about 10^17 seconds. It is just not practical to omptimize the layout like that. And having all gates in blocks gets us very acceptable local optima anyways (gates inside a block tend to be more interconnected with each other most of the cases) EDIT: clarification