Verilog has many drawbacks, including no support for structured signals. On the other hand, the other big language, VHDL, is really difficult to use for "modul

Verilog has many drawbacks, including no support for structured signals. On the other hand, the other big language, VHDL, is really difficult to use for "modular" projects. Is anyone here familiar with CHDL, a C++ hardware design language? https://github.com/cdkersey/chdl https://github.com/cdkersey/chdl Being a fan of C++ myself, the idea of using template metaprogramming to represent hardware designs is something that I think is very cool.