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I designed a Pipelined MIPS processor in Verily during undergrad. It was probably the hardest and most rewarding task I've completed in my life! https://github
by eggie5 10y ago
I designed a Pipelined MIPS processor in Verily during undergrad. It was probably the hardest and most rewarding task I've completed in my life!
https://github.com/eggie5/SDSU-COMPE475-SPRING13 https://github.com/eggie5/SDSU-COMPE475-SPRING13
- GrumpyYoungMan 10y agoHDLs and FPGAs, such luxury. In my undergraduate days, we had to design a 32-bit processor by laying out individual transistors by hand (n-wells, p-wells, polysilicon gates, and metallization layers) in a 25 micron CMOS process with two metallization layers in very little chip area and then prove that it worked in simulation. It was like Tetris from hell; I'm still proud of the compact barrel shifter design I came up with. We also had the option, which I will forever regret not taking, to have the chip physically fabbed as well, as long as we agreed to do the work to validate it afterward.
- eggie5 10y agohaha, respect.