3 ms·
> You're talking about RTL, which is exactly what these languages output. If VHDL/Verilog would output RTL, you could easily analyze it just as you analyze ass
by wolfgke 10y ago
> You're talking about RTL, which is exactly what these languages output.
If VHDL/Verilog would output RTL, you could easily analyze it just as you analyze assembly output of your favorite compiler. Unluckily the output is some proprietary bitstream for the FPGA.
- vvanders 10y agoIt's been a while since I poked around in RTL but last time I was working with FPGAs it was possible to inspect RTL and view the synthesis results.
- k0ngo 10y agoJust as a software compilation flow is devided into preprocessing, compilation, assembly, and linking, a HDL flow is divided into synthesis, mapping, place and route, timing analysis and bitstream generation. RTL is the output of the synthesis stage and is readily available to the designer, typically both as code and as a graphical schematic.
- deleted 10y ago[deleted]