4 ms·
To look at it another way, what does one gain? Hardware is highly parallelizable and HDLs give you that capability by default. Verilog is a really easy language
by blackguardx 10y ago
To look at it another way, what does one gain? Hardware is highly parallelizable and HDLs give you that capability by default. Verilog is a really easy language to learn. The hard part is learning how to do hardware design.
- noescape 10y agoOne gains not needing to learn another language. I know C, I don't know Verilog or VHDL. I know how to debug C, I don't know how to debug Verilog. If I can write a working C program, why can't I make working hardware?
- blackguardx 10y agoKnowing how to debug C won't help you. There is no state machine running your code. Stepping through instructions doesn't apply. Debugging HDL involves looking at timing waveforms in a simulator.
- noescape 10y agoCould one write a state machine running the code? VMs do.