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These objections don't totally match my limited experience (not done this in a long time). When I did a lot of HDL work, I found that the main challenge was to
by shubb 10y ago
These objections don't totally match my limited experience (not done this in a long time). When I did a lot of HDL work, I found that the main challenge was to stop thinking of hardware design like programming.
This is why dynamic typing (even if it is static type inference) is a bad idea in the hardware world. Embedded software programmers want C style types because they are often flipping bits or packing data into a specified data structure so that some hardware that expects particular bytes in particular places knows where to get it. In HDL, you are fitting your logic into very limited space, and need to constantly keep in mind what hardware the code you are writing is going to synthesize to.
Later, I realized that HDLs are often not really used like we'd think. Having written the logic in C or maybe Verilog, a lot of shops figure out what the actual desired hardware is and write verilog to specify that. So in verilog, rather than getting the compiler to infer a flipflop you can specify one and use verlilog to wire it up. Professional shops often basically use verilog to describe a circuit design in text, like a C programmer dropping into assembly.
The thing is that, like in the 1980s, you are so much fighting to get the fastest, smallest implementation possible, that like an 80s programmer, many default to assembly - to specifying the logic elements rather than leaving it to a compiler.
That means verilog as written many places is not really used like verilog at all - more like using verilog to express a netlist. Verilog is used to wrap vendor specific code so you specify a flipflop rather than a Xilinx flipflop, to make it easier to go to another vendor or to ASIC, but the clever features of verilog are only used for your test harnesses.
Part of the reason for this is that FPGAs are full of specific purpose hardware like dual port memories, and the compiler won't always infer them for you. That means you need to explicitly tell it to use them - and once you are explicitly specifying some parts of your system, you tend to do it more and more.
- wolfgke 10y ago> Part of the reason for this is that FPGAs are full of specific purpose hardware like dual port memories, and the compiler won't always infer them for you. You can only use a HLL if you can rely on the fact that the compiler will nearly always put out much better code than you would be able to invent in a reasonable amount of time. This is the reason why even in the late 90th for performance-intensive code (games, multimedia) the critical parts were often still written in assembly instead of C/C++. The problem is for FPGAs the bitstream format is very closed - so you can hardly dive into the low-level abyss and "look at the generated assembly code/bistream" to rewrite the generated assembly code/bitstream code until you are satisfied with the result; you have to use the HLL (VHDL/Verilog), where you cannot trust the quality of the generated code.
- blackguardx 10y agoInstead of looking at the "assembly" or bistream, FPGA and ASIC designers use a graphical tool to look at the inferred hardware blocks. There are also tools to visualize how these blocks are placed on the die/FPGA.