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So they have an LLVM target for RISC-V. They could submit that but they choose to divide it up into pieces and submit them piecemeal. This is the first piece of
by CalChris 10y ago
So they have an LLVM target for RISC-V. They could submit that but they choose to divide it up into pieces and submit them piecemeal. This is the first piece of that meal. If you want to skip to the dessert:
https://github.com/riscv/riscv-llvm https://github.com/riscv/riscv-llvm
- eliben 10y ago> They could submit that but they choose to divide it up into pieces and submit them piecemeal It's common practice in OSS to request splitting of large patches into smaller as-much-self-contained-as-possible pieces, to make reviewing more feasible. Same goes for non-OSS products in companies with good development practices, I guess.
- legulere 10y agoIt's actually a reimplementation, because there were some (I think legal) problems with the implementation that you linked
- CalChris 10y agoThanks. That sounds similar to the GCC kerfuffle.
- asb 10y agoPlease see here for background on the effort: http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.html http://lists.llvm.org/pipermail/llvm-dev/2016-August/103748.... I believe that given RISC-V's status as a clean and open ISA, the RISC-V port for any project should be the most accessible, best documented and cleanest. I am attempting to pursue this for the LLVM port. This has real practical benefit - the easier it is for research groups and hobbyists to hack on the RISC-V LLVM backend, the easier it is to perform interesting hardware/software co-design and architectural research.