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The semiconductor manufacturing processes might be flatlining a bit, but that's not entirely synonymous with "computer technology". One recent example we've alr

by peller 10y ago

The semiconductor manufacturing processes might be flatlining a bit, but that's not entirely synonymous with "computer technology". One recent example we've already witnessed was in the GPU sector. They (nVidia and AMD) were stuck on 28nm for at least 5 years, and instead of just being able to rely on the "standard improvements" (by way of Moore's law) to get better performance at lower power, they had to rely on architectural improvements. nVidia fared significantly better, managing to double performance-per-watt on the same manufacturing node with Maxwell (GTX 980). Is such a feat easily repeatable? Very unlikely. But it also goes to show that when these companies can rely on improvements in the manufacturing process for their speed/efficiency boosts, they don't necessarily put as much effort into architectural improvements as they otherwise might. If you haven't heard of the Mill CPU, it's one example of completely rethinking things: http://millcomputing.com/docs/belt/ http://millcomputing.com/docs/belt/ Of course, the problem there is the missing software/OS toolchain. But it also points towards there being some huge inefficiencies present in "classic" von Neumann architectures, and to me, the possibility that there's still room for things to improve.

XorNot 10y ago
The Mill is far from proven. It's a big idea, but big ideas always look good initially - it's when you get down to the implementation details that most of your revolution in something tends to dry up and just become an evolutionary improvement in performance.
paulmd 10y ago
The next "total rethink" of GPUs is multiple dies on a single package. Not just for HBM, there's no reason you can't have the dies "hanging off" the interposer (supported by an inactive substrate), only overlapping the interposer on the regions necessary for chip bumps. Essentially each die becomes a large SMX Engine or other hierarchal unit that is marshalled by some central memory controller or other controller that presents the illusion of a single GPU rather than SLI/Crossfire. This is actually the direction AMD is going with Navi, not because of the performance gains per se but because it helps yields big time. You can pre-bin your chips, then stitch a bunch of small chips into medium chips while keeping your yields high. In theory you can scale up for quite a while. At the long term, you will eventually be limited by clock degradation/signal propagation time however. The short-term problem is heat and power. This doesn't help efficiency gains per se. If you are stitching together four 600mm^2 dies then you are going to be pulling 1000-1200W and dumping that back out into your cooling system. For US consumers, their circuit breakers are a much more immediate limit. Most household circuits are 15A @ 120V, and that's an instantaneous limit. You are not supposed to continuously pull more than 80% of a circuit's instantaneous rating, so that's 12A (1440W at the wall). Factor in the losses from the PSU's 80% efficiency and you are now talking 1152W continuously. Again, that works out to about four 600mm^2 GPU dies, plus some power budget for the CPU and so on. And you'd probably need to take drastic measures to keep that cool - that's a lot of heat in a small surface area.
renox 10y ago
> the possibility that there's still room for things to improve. Of course but notice that your desktop computer is using an x86 ISA instead of a RISC ISA because in many case backward compatibility and network effect trump performance improvement..

by peller 10y ago

XorNot 10y ago

The Mill is far from proven. It's a big idea, but big ideas always look good initially - it's when you get down to the implementation details that most of your revolution in something tends to dry up and just become an evolutionary improvement in performance.

paulmd 10y ago

The next "total rethink" of GPUs is multiple dies on a single package. Not just for HBM, there's no reason you can't have the dies "hanging off" the interposer (supported by an inactive substrate), only overlapping the interposer on the regions necessary for chip bumps. Essentially each die becomes a large SMX Engine or other hierarchal unit that is marshalled by some central memory controller or other controller that presents the illusion of a single GPU rather than SLI/Crossfire. This is actually the direction AMD is going with Navi, not because of the performance gains per se but because it helps yields big time. You can pre-bin your chips, then stitch a bunch of small chips into medium chips while keeping your yields high. In theory you can scale up for quite a while. At the long term, you will eventually be limited by clock degradation/signal propagation time however. The short-term problem is heat and power. This doesn't help efficiency gains per se. If you are stitching together four 600mm^2 dies then you are going to be pulling 1000-1200W and dumping that back out into your cooling system. For US consumers, their circuit breakers are a much more immediate limit. Most household circuits are 15A @ 120V, and that's an instantaneous limit. You are not supposed to continuously pull more than 80% of a circuit's instantaneous rating, so that's 12A (1440W at the wall). Factor in the losses from the PSU's 80% efficiency and you are now talking 1152W continuously. Again, that works out to about four 600mm^2 GPU dies, plus some power budget for the CPU and so on. And you'd probably need to take drastic measures to keep that cool - that's a lot of heat in a small surface area.

renox 10y ago

> the possibility that there's still room for things to improve. Of course but notice that your desktop computer is using an x86 ISA instead of a RISC ISA because in many case backward compatibility and network effect trump performance improvement..