4 ms·
If you know how memory addresses map to row/column, it should be possible to force refresh the entire array with a few tens of thousands of reads, rather than d
by ta161028 10y ago
If you know how memory addresses map to row/column, it should be possible to force refresh the entire array with a few tens of thousands of reads, rather than delaying for 64ms. (At least on conventional DRAM, reading a row implicitly refreshes it; I presume it's the same on DDR SDRAM.)
- PhantomGremlin 10y agoYes, I just posted this in somewhat greater detail. https://news.ycombinator.com/item?id=12821946 https://news.ycombinator.com/item?id=12821946 There are a lot of details to consider. E.g. reading DRAM (rather than from on-chip cache) consumes a lot more power, which could be quite harmful on a laptop.
- salessawi 10y agoA very similar approach, that attempts to refresh rows adjacent to the ones that are being repeatedly accessed is described here(disclosure: I am one of the authors of the paper): Paper: https://iss.oy.ne.ro/ANVIL.pdf https://iss.oy.ne.ro/ANVIL.pdf Kernel Module Code: https://github.com/zaweke/rowhammer/tree/master/anvil https://github.com/zaweke/rowhammer/tree/master/anvil It is tested on on an Intel SandyBridge CPU. For a full deployment, we would need to know which bits of the physical address are used to select the DRAM banks and rows for each specific CPU. There has been some effort to reverse engineer these mappings by various people. Two excellent sources regarding these mappings: http://lackingrhoticity.blogspot.com/2015/05/how-physical-addresses-map-to-rows-and-banks.html http://lackingrhoticity.blogspot.com/2015/05/how-physical-ad... https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_pessl.pdf https://www.usenix.org/system/files/conference/usenixsecurit...
- antocv 10y agoThis, this is the real golden solution. Thank you for your work and links, so full of information, golden, golden!