In my experience, hardware is much more difficult to debug. But my hardware experience is limited to FPGAs, never a full ASIC team. There are nightmarish bugs i

In my experience, hardware is much more difficult to debug. But my hardware experience is limited to FPGAs, never a full ASIC team. There are nightmarish bugs in hardware associated with things like clock domain crossings, bad timing constraints, and signal integrity. Give me software bugs over that any day!