4 ms·
I will respectfully disagree :). We have taken Intel's reference code (https://github.com/lukego/intel-ipsec/blob/master/code/avx2/gcm_avx_gen4.asm https://git
by lukego 10y ago
I will respectfully disagree :).
We have taken Intel's reference code (https://github.com/lukego/intel-ipsec/blob/master/code/avx2/gcm_avx_gen4.asm https://github.com/lukego/intel-ipsec/blob/master/code/avx2/...) for high-speed AES-GCM encryption and used DynASM (https://luajit.org/dynasm.html https://luajit.org/dynasm.html) to refactor it as a much smaller program (https://github.com/snabbco/snabb/blob/master/src/lib/ipsec/aes_128_gcm_avx.dasl https://github.com/snabbco/snabb/blob/master/src/lib/ipsec/a...). I see this as highly worthwhile: we are working on making the software ecosystem simpler and tighter just because we are hackers, while Intel are working primarily on selling CPUs and whatever is best for their bottom line.
I disagree with this characterization of DDIO but I don't think Hacker News comments is the best venue for such low-level discussions. Hope to chat with you about it in some more suitable forum some time :) that would be fun.
- JoachimSchipper 10y agoFWIW, I would be quite interested in your view on DDIO - anything you can link?
- lukego 10y agoIntel DDIO FAQ: http://www.intel.com/content/dam/www/public/us/en/documents/faqs/data-direct-i-o-faq.pdf http://www.intel.com/content/dam/www/public/us/en/documents/... My understanding is that DDIO is an internal feature of the processor and works transparently with all PCI devices. Basically Intel extended the processor "uncore" to serve PCIe DMA requests via the L3 cache rather than directly to memory.