When I first heard about the co-processor extensions in ARM, I spent hours dreaming up a dynamic FPGA accelerated co-processor that could have dynamic 'instruct

When I first heard about the co-processor extensions in ARM, I spent hours dreaming up a dynamic FPGA accelerated co-processor that could have dynamic 'instructions' swapped in based on typical work loads it was receiving. The compiler would generate the custom HW FPGA programs based on profiling data from previous iterations of the app and static inspections - the dynamic complex blocks then attached to the ELF for loading. A statistics block in the CPU determines which ones are loaded via a kernel driver (I think you could do with with pure SW actually - no HW support needed) - you'd need a "branch if instruction-X is available" and I guess some interlocks to stop instructions being swapped out until the SW has finished with them etc... I may dream, but this team did it! Super cool. Having spent a day with Zynq trying to load bitstreams from Linux running on the hard cores (and completely failing such that I changed attack vector) this alone is impressive :)