4 ms·
Also worth noting: x86 supports four hardware breakpoints, which are sometimes more convenient, since they don't involve overwriting any instructions. (They're
by pcwalton 10y ago
Also worth noting: x86 supports four hardware breakpoints, which are sometimes more convenient, since they don't involve overwriting any instructions. (They're also more flexible because they can be used to trap on memory reads, etc.) https://en.wikipedia.org/wiki/X86_debug_register https://en.wikipedia.org/wiki/X86_debug_register
- wazari972 10y agoI thought that these HW 'breakpoint' registers were (only) used to implement watchpoint, that is, read/write operations on data. Can they be used to implement 'instruction breakpoints'?
- jasonzemos 10y agoOn register %dr7 there are 4-bit switches for each of the 4 breakpoints. The first two bits can trap on Instruction (0b00), Write (0b01), and ReadWrite (0b11). The second two bits specify the alignment of Byte (0b00), Short (0b01), Long (0b10), and Int (0b11).
- pcwalton 10y agoYou can set the "break on" bitfield to "execute" (0) to have the debug register function as a normal breakpoint.
- burfog 10y agoSure, but normally you wouldn't waste them on that. You might use them for instruction breakpoints in ROM, or when you suspect that the program checksums itself.
- EvanAnderson 10y agoI remember the first time I read about the hardware-based debugging functionality in the 80386 and being in awe. I'd programmed 6502 and 8086 assembler and was just blown-away by the treasure-trove of debugging functionality the '386 had available to it. It seemed like it was just short of an in-circuit emulator and so very, very cool.
- compiler-guy 10y agoIt's not just x86, pretty much every modern architecture has hardware breakpoint registers, data watch point registers and so on.