I've only ever used the low end tools for FPGA parts, but even when you design with an HDL, the output is realized in stages. It translates your code, then

I've only ever used the low end tools for FPGA parts, but even when you design with an HDL, the output is realized in stages. It translates your code, then determines a netlist, then does physical layout and routing, then it can produce either a bitstream output for something like an FPGA, or one of several outputs that can be sent to a fabrication plant for ASIC production. For the image processing "state machine" I imagine most of the "core" design is done at the HDL level with some small tweaks to the other steps along the way to optimize the chip for physical production.