> That's super interesting, so I know there is no point in trying to improve the alignment too much. Typical x86 cache line size is 64B, AVX registers are 32B.

> That's super interesting, so I know there is no point in trying to improve the alignment too much. Typical x86 cache line size is 64B, AVX registers are 32B. When your o pointer isn't 32B-aligned, you are loading across cache line boundary every second time. If nkurz is right and this loop can run 1 iteration per cycle, misalignemnt probably slows it down to 2i/3c. Benchmark this loop if you want to know. Of course it only matters if the array is still in L1, maybe L2 (?). edit: Not exactly 2i/3c, see http://www.agner.org/optimize/blog/read.php?i=415#423 http://www.agner.org/optimize/blog/read.php?i=415#423