4 ms·
On recent processors (last few years), as long as you're not crossing a cache line, unaligned is essentially the same as aligned in terms of performance.
by zbjornson 10y ago
On recent processors (last few years), as long as you're not crossing a cache line, unaligned is essentially the same as aligned in terms of performance.
- 737774 10y agoOh wow - how is that achieved? I've spent my career in mobile and didn't know this was true on desktop
- stephencanon 10y agoThis is true on modern mobile CPUs, too. ARMv8 doesn't even have explicit aligned vector loads.
- antirez 10y agoOh! That's super interesting, so I know there is no point in trying to improve the alignment too much. I'll try anyway if I can make the whole operation a linear scan but if there is no big penalty, to add padding among weights looks like a bad idea.
- qb45 10y ago> That's super interesting, so I know there is no point in trying to improve the alignment too much. Typical x86 cache line size is 64B, AVX registers are 32B. When your o pointer isn't 32B-aligned, you are loading across cache line boundary every second time. If nkurz is right and this loop can run 1 iteration per cycle, misalignemnt probably slows it down to 2i/3c. Benchmark this loop if you want to know. Of course it only matters if the array is still in L1, maybe L2 (?). edit: Not exactly 2i/3c, see http://www.agner.org/optimize/blog/read.php?i=415#423 http://www.agner.org/optimize/blog/read.php?i=415#423