5 ms·
Part 1: 50% applies, RAM controllers now part of the CPU, deprecating half of what’s written, also some CPUs have eDRAM. Part 2: almost completely applies. Part
by Const-me 10y ago
Part 1: 50% applies, RAM controllers now part of the CPU, deprecating half of what’s written, also some CPUs have eDRAM.
Part 2: almost completely applies.
Part 3: 70% applies, hardware SLAT (Intel EPT / AMD RVI) deprecated what’s written about virtualization.
Part 5: 90% applies.
The rest of them — don’t know.
P.S. What’s I dislike most about the article, it fails to explain why L3 cache is 10-20 times slower than L1 cache, while they both made from SRAM.
- nateberkopec 10y ago> it fails to explain why L3 cache is 10-20 times slower than L1 cache, while they both made from SRAM. Why is it? Is it because L3 is usually shared?
- Const-me 10y agoEven when the cache line is unshared, L3 is still 10 times slower than L1. The best explanation I saw is this: https://fgiesen.wordpress.com/2016/08/07/why-do-cpus-have-multiple-cache-levels/ https://fgiesen.wordpress.com/2016/08/07/why-do-cpus-have-mu...
- bogomipz 10y agoI think generally the larger the cache the higher the latency. I think various factor are things like available power budget, some increase in signal propagation delay and more complicated logic needed in a larger search space.
- Alphasite_ 10y agoWithout having read the article I assume it is something to do with the asseociscativity and size of it?