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Instead of memorizing tables, it would be more valuable to programmers to read how these numbers come to be in the first place. An excellent, and much longer re
by eatbitseveryday 10y ago
Instead of memorizing tables, it would be more valuable to programmers to read how these numbers come to be in the first place. An excellent, and much longer read, is by Ulrich Drepper[1].
[1] http://lwn.net/Articles/250967/ http://lwn.net/Articles/250967/
- tayo42 10y agoI came across this article the other day for the first time and started to read it. How much still applies to today?
- a3n 10y agoThings haven't changed much since the other day, so probably all of it.
- cornstalks 10y agoGP probably didn't mean "9 years ago" (the article was published over 9 years ago) when saying "the other day." 9 years is a long time in the tech world. It's a valid question.
- honkhonkpants 10y agoWhy do you say so? AMD k8 came out 14 years ago and PC architecture is basically unchanged since.
- alcari 10y agoFrom a quick look through, most of it. Modern x86 micro-architectures still use integrated memory controllers and ~3 level CPU caches. All the timings are a little faster, the caches a little bigger, and the buses a little wider, but it's still basically the same stuff with different names.
- Const-me 10y agoPart 1: 50% applies, RAM controllers now part of the CPU, deprecating half of what’s written, also some CPUs have eDRAM. Part 2: almost completely applies. Part 3: 70% applies, hardware SLAT (Intel EPT / AMD RVI) deprecated what’s written about virtualization. Part 5: 90% applies. The rest of them — don’t know. P.S. What’s I dislike most about the article, it fails to explain why L3 cache is 10-20 times slower than L1 cache, while they both made from SRAM.
- nateberkopec 10y ago> it fails to explain why L3 cache is 10-20 times slower than L1 cache, while they both made from SRAM. Why is it? Is it because L3 is usually shared?
- Const-me 10y agoEven when the cache line is unshared, L3 is still 10 times slower than L1. The best explanation I saw is this: https://fgiesen.wordpress.com/2016/08/07/why-do-cpus-have-multiple-cache-levels/ https://fgiesen.wordpress.com/2016/08/07/why-do-cpus-have-mu...
- bogomipz 10y agoI think generally the larger the cache the higher the latency. I think various factor are things like available power budget, some increase in signal propagation delay and more complicated logic needed in a larger search space.
- Alphasite_ 10y agoWithout having read the article I assume it is something to do with the asseociscativity and size of it?
- bogomipz 10y agoI think its less important to know the exact numbers since those are a moving target but its more important to understand the orders of magnitude in difference from fastest to slowest and in between.
- bastijn 10y agoI browsed the comments hoping there would be a better alternative in the comments. Could not have hoped to find a better article. Thank you, the first two chapters are a great read. Bookmarked for the weekend. On the date of publication and rapid changes in tech world. It might be a bit older but the generic concepts are still great to learn if you only heard the terms before but don't know the details.
- CalChris 10y agoPDF version of said same article. https://www.akkadia.org/drepper/cpumemory.pdf https://www.akkadia.org/drepper/cpumemory.pdf Need to supplement this excellent article with Row Hammer information. It doesn't cover clflush. I sent the author a note.
- rshaban 10y ago"The original document prints out at over 100 pages." - for reference