3 ms·

So what can we count on? In a tile based CPU error topology matters. A string of broken cores or a broken core at the edges is likely worse than a broken core

• adapteva 10y ago
  Impossible to characterize without high volume silicon or accurate yield models. We can say that historically, most failures are in SRAM cells and they are limited to a few bits (core still works!) and that in general only one out of N cores will fail. For arguments sake, let's assume the while network always works, but 1 CPU may be broken. (this is what needs to be confirmed later). Does that help?
  • vardump 10y ago
    Yes, that helps. It might be easier to work around broken SRAM bits than just skipping a whole core. That way you could always have same pipeline layout and not need to compute it dynamically.