5 ms·

RTL = Register Transfer Logic, and EDA = Electronic Design Automation, for anyone else who was curious. I don't know what GDS stands for, but context indicates

RTL = Register Transfer Logic, and EDA = Electronic Design Automation, for anyone else who was curious. I don't know what GDS stands for, but context indicates it's the actual physical description that's used to make the part. But I'm confused about what part of this is open and not open. Do they mean that they imported their Verilog into a proprietary tool, which generates the design? That doesn't make it open source in practice.

adapteva 10y ago
HW design is not that different from SW design. Comp table below: HW SW Verilog --> C/Java/etc EDA --> GCC/LLVM GDS --> Binary (elf) The GDS is completely tied up in NDAs due to the foundry. The EDA combines/translates open source code with proprietary blobs to produce a "super secret" GDS binary blob that gets sent to the foundry for manufacturing.
- LukeShu 10y ago
  For anyone else who was confused by everything being on one line: HW SW Verilog --> C/Java/etc EDA --> GCC/LLVM GDS --> Binary (elf)
  - NEDM64 10y ago
    For everyone still confused Verilog --> imperative language EDA --> IDE + compiler GDS --> Assembly
- ChrisRus 10y ago
  > HW design is not that different from SW design. Shouldn't be. But it is.
  - AceJohnny2 10y ago
    Except the economics are vastly different. The complexity and cost of manufacturing, the computationally intensive cost of simulation and various checks and optimizations (be it clock timing or mask optimizations to etch features that are smaller than the wavelength used to etch them), all mean that you can't just "compile and publish", and turnaround times are months, not hours. And there are no open-source toolchains for any of this. It's a student project to implement a SW compiler, why isn't it to implement an RTL compiler?
    - zanny 10y ago
      Nothing about the time frames or even production costs justify the disparity in how proprietary and closed hardware manufacturing is. For the exact reason hardware and software are different open sourcing your patterning toolchain has nothing to do with your competitive advantage in actually having built foundries with functioning lithography. The cost is in the later, the former is just abuse of position for power over the end user. If anything, it hurts your bottom line. You would probably get more third party interest in having print outs of custom hardware if the toolchains were more open. It is not a question of price, its a question of exposure. I'm not even talking about the 12-20nm stuff. It is still crazy expensive because the hardware and software R&D was huge and these companies are hoarding their toys like preschoolers because of a prisoners dilemma in regards to competitive advantage. But older 45-100nm plants are often still in use but are still just as inaccessible as ever to most hobbyist hardware enthusiasts.
      - AceJohnny2 10y ago
        > The cost is in the latter, the former is just abuse of position for power over the end user. Exactly, hence my question about "student projects" which is really about why aren't there more OSS projects that challenge this. Is it because of the lack of platforms to experiment on, or the inherent difficulty of the task?
        seanp2k2 10y ago
        Thinking about this, yeah it'd be amazing to e.g. Have a community-driven forum with some DIY CPU designs (lisp machines!) with an affordable (let's say under $1k per chip) way to get them made. We'll probably get there eventually, but I'm not aware of where progress on this front is.
      - Klinky 10y ago
        If it was really that easy then hobbyists would have found a way to do it on their own by now(e.g. 3D printing). You can't just demand that someone open their billion dollar fabs to amateur hobbyists. It is very likely if the fab is still operating at a certain process, it's because they have profitable business churning through it. If it's not profitable, they retool or close it down. An idle fab is money down the drain, and it's really doubtful hobbyists would be able to fill the gap with a bunch of one-off production runs, while likely needing a lot of hand holding. Custom circuit boards are coming down in price, maybe custom lithography will come down in price at some point to be accessible to hobbyists / startups.
  - analognoise 10y ago
    I don't see how it shouldn't be; it's an entirely different set of constraints?
    - NEDM64 10y ago
      Yes, it is. Specially when you're working with RF or when you're doing commercial products or when you have a strict timeline and limited resources. In a software project, the development is only limited by the Human Resources, you can't realistically blame the computer for being too slow to compile your code, and there are no "defects" when your users download your code.
- signa11 10y ago
  > HW design is not that different from SW design. reminds me of alan-kay's comment "hardware is just software which has crystallized early"
avip 10y ago
Graphic Data System. AKA GDSII
bobmoretti 10y ago
Probably RTL would be more correctly known as "Register Transfer Level" as in a level of abstraction, in contrast to for example the lower "gate" level of abstraction.
iheartmemcache 10y ago
The limiting factor is your 'building blocks' (component libraries with things their cells, IO and what-have-you)) that your fab (i.e. TSMC) gives to your design software house (e.g. Mentor, Synopsis, Cadence) for a specific process (e.g. $integer-$um|nm CMOS) for a production run is usually built off of heavily NDA'd building blocks locked down by contract[0] (and that's assuming you have the cash to to buy time for that tape out!). Even designing simple stuff without the fab's component libraries for old processes would be a daunting task. (For some context, something circa the Sega Dreamcast era -- 350 nm/4 layers or there abouts -- is well in the realm of what an undergraduate would be able to design with a fair bit of ease for his capstone (senior-year) project is doable by a talented single 4th year with the component libs. Without the tooling, he'd be lost.) I'm sure Adapteva wanted to open source their final files which went to the fab for tape-out, but you could bet your bottom dollar if they did, a take-down letter would be sent to Github and Adapteva would be slammed with a lawsuit. SPICE is/was the original open-source project that came out of UC Berkeley in the '70s if you want to go from zero-to-tape-out on an entirely open source stack but it's no trivial task. http://opencircuitdesign.com/links.html http://opencircuitdesign.com/links.html has some auxiliary resources, and IIRC there's a Linux distribution with a pretty good toolkit with even things like analog simulators for RFIC (though, as the late-great Bob Pease of NatSemi said - "never trust the simulator" ;)). Side-note: Adapteva - your work is fascinating, so much so that I read your entire set of ref docs for the Epiphany. I'm in the Boston area, let me buy y'all a coffee at Diesel as I'd love to pick you brains. -- [0] - (Grey area legality content) - Here's an example of the documentation of the libs you'd be using - normally even these documents are lock&keyed: http://www.utdallas.edu/~mxl095420/EE6306/Final%20project/tsmc18_component.pdf http://www.utdallas.edu/~mxl095420/EE6306/Final%20project/ts... This looks like a masters level thesis project directory by the course number (didn't go to U of T:D) @ 180 nm sizing.

adapteva 10y ago

HW design is not that different from SW design. Comp table below: HW SW Verilog --> C/Java/etc EDA --> GCC/LLVM GDS --> Binary (elf) The GDS is completely tied up in NDAs due to the foundry. The EDA combines/translates open source code with proprietary blobs to produce a "super secret" GDS binary blob that gets sent to the foundry for manufacturing.

LukeShu 10y ago
For anyone else who was confused by everything being on one line: HW SW Verilog --> C/Java/etc EDA --> GCC/LLVM GDS --> Binary (elf)
- NEDM64 10y ago
  For everyone still confused Verilog --> imperative language EDA --> IDE + compiler GDS --> Assembly
ChrisRus 10y ago
> HW design is not that different from SW design. Shouldn't be. But it is.
- AceJohnny2 10y ago
  Except the economics are vastly different. The complexity and cost of manufacturing, the computationally intensive cost of simulation and various checks and optimizations (be it clock timing or mask optimizations to etch features that are smaller than the wavelength used to etch them), all mean that you can't just "compile and publish", and turnaround times are months, not hours. And there are no open-source toolchains for any of this. It's a student project to implement a SW compiler, why isn't it to implement an RTL compiler?
  - zanny 10y ago
    Nothing about the time frames or even production costs justify the disparity in how proprietary and closed hardware manufacturing is. For the exact reason hardware and software are different open sourcing your patterning toolchain has nothing to do with your competitive advantage in actually having built foundries with functioning lithography. The cost is in the later, the former is just abuse of position for power over the end user. If anything, it hurts your bottom line. You would probably get more third party interest in having print outs of custom hardware if the toolchains were more open. It is not a question of price, its a question of exposure. I'm not even talking about the 12-20nm stuff. It is still crazy expensive because the hardware and software R&D was huge and these companies are hoarding their toys like preschoolers because of a prisoners dilemma in regards to competitive advantage. But older 45-100nm plants are often still in use but are still just as inaccessible as ever to most hobbyist hardware enthusiasts.
    - AceJohnny2 10y ago
      > The cost is in the latter, the former is just abuse of position for power over the end user. Exactly, hence my question about "student projects" which is really about why aren't there more OSS projects that challenge this. Is it because of the lack of platforms to experiment on, or the inherent difficulty of the task?
      - seanp2k2 10y ago
        Thinking about this, yeah it'd be amazing to e.g. Have a community-driven forum with some DIY CPU designs (lisp machines!) with an affordable (let's say under $1k per chip) way to get them made. We'll probably get there eventually, but I'm not aware of where progress on this front is.
    - Klinky 10y ago
      If it was really that easy then hobbyists would have found a way to do it on their own by now(e.g. 3D printing). You can't just demand that someone open their billion dollar fabs to amateur hobbyists. It is very likely if the fab is still operating at a certain process, it's because they have profitable business churning through it. If it's not profitable, they retool or close it down. An idle fab is money down the drain, and it's really doubtful hobbyists would be able to fill the gap with a bunch of one-off production runs, while likely needing a lot of hand holding. Custom circuit boards are coming down in price, maybe custom lithography will come down in price at some point to be accessible to hobbyists / startups.
- analognoise 10y ago
  I don't see how it shouldn't be; it's an entirely different set of constraints?
  - NEDM64 10y ago
    Yes, it is. Specially when you're working with RF or when you're doing commercial products or when you have a strict timeline and limited resources. In a software project, the development is only limited by the Human Resources, you can't realistically blame the computer for being too slow to compile your code, and there are no "defects" when your users download your code.
signa11 10y ago
> HW design is not that different from SW design. reminds me of alan-kay's comment "hardware is just software which has crystallized early"

avip 10y ago

Graphic Data System. AKA GDSII

bobmoretti 10y ago

Probably RTL would be more correctly known as "Register Transfer Level" as in a level of abstraction, in contrast to for example the lower "gate" level of abstraction.

iheartmemcache 10y ago

The limiting factor is your 'building blocks' (component libraries with things their cells, IO and what-have-you)) that your fab (i.e. TSMC) gives to your design software house (e.g. Mentor, Synopsis, Cadence) for a specific process (e.g. $integer-$um|nm CMOS) for a production run is usually built off of heavily NDA'd building blocks locked down by contract[0] (and that's assuming you have the cash to to buy time for that tape out!). Even designing simple stuff without the fab's component libraries for old processes would be a daunting task. (For some context, something circa the Sega Dreamcast era -- 350 nm/4 layers or there abouts -- is well in the realm of what an undergraduate would be able to design with a fair bit of ease for his capstone (senior-year) project is doable by a talented single 4th year with the component libs. Without the tooling, he'd be lost.) I'm sure Adapteva wanted to open source their final files which went to the fab for tape-out, but you could bet your bottom dollar if they did, a take-down letter would be sent to Github and Adapteva would be slammed with a lawsuit. SPICE is/was the original open-source project that came out of UC Berkeley in the '70s if you want to go from zero-to-tape-out on an entirely open source stack but it's no trivial task. http://opencircuitdesign.com/links.html http://opencircuitdesign.com/links.html has some auxiliary resources, and IIRC there's a Linux distribution with a pretty good toolkit with even things like analog simulators for RFIC (though, as the late-great Bob Pease of NatSemi said - "never trust the simulator" ;)). Side-note: Adapteva - your work is fascinating, so much so that I read your entire set of ref docs for the Epiphany. I'm in the Boston area, let me buy y'all a coffee at Diesel as I'd love to pick you brains. -- [0] - (Grey area legality content) - Here's an example of the documentation of the libs you'd be using - normally even these documents are lock&keyed: http://www.utdallas.edu/~mxl095420/EE6306/Final%20project/tsmc18_component.pdf http://www.utdallas.edu/~mxl095420/EE6306/Final%20project/ts... This looks like a masters level thesis project directory by the course number (didn't go to U of T:D) @ 180 nm sizing.