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You refer to the per-CPU SRAM as "memory" rather than "cache". It's just addressable local memory? How many DRAM ports?
by ScottBurson 10y ago
You refer to the per-CPU SRAM as "memory" rather than "cache". It's just addressable local memory?
How many DRAM ports?
- adapteva 10y agoYes, you can call it scratchpad or sram. The point is that there is no hardware caching. The local SRAM is split into 4 separate banks so it is "effectively" 4 ported. DRAM controllers is up to the system designer. This is handled by the FPGA. (like previous epiphany chips).