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Two things immediately jump out Custom ISA extensions for deep learning, communication, and cryptography DARPA/MTO autonomous drones cognitive radi

Two things immediately jump out Custom ISA extensions for deep learning, communication, and cryptography DARPA/MTO autonomous drones cognitive radio The radar geeks are gonna love to get their hands on ~250GFLOP, 4watt processor.

microcolonel 10y ago
Could be excellent for a dense automatic isolating array microphone; thousand other things. I'd love to see Parallella in embedded, they set a great example.
nickpsecurity 10y ago
I'm seeing NIDS for 10+Gbit links, DDOS mitigation, cache appliance for web servers, Erlang accelerator, BitTorrent accelerator, and so on. Quite a few possibilities. Also, something like this might be tuned for hardware synthesis, formal verification, or testing given all the resources that requires. Intel has a nice presentation showing what kind of computing resources go into their CPU work: https://www-ssl.intel.com/content/dam/www/public/us/en/documents/white-papers/intel-it-hpc-silicon-design-paper.pdf https://www-ssl.intel.com/content/dam/www/public/us/en/docum...
- valarauca1 10y ago
  I don't believe the chip has enough I/O for a 10Gb nic.
  - adapteva 10y ago
    The issue is not bandwidth, it's the system cost. The chip has 1024 IO pins. (more than enough for MANY 10Gb nics...)
    - nickpsecurity 10y ago
      "The issue is not bandwidth, it's the system cost." What does that mean?
mamcx 10y ago
I have a naive question based in my dreams: Is possible to design a CPU that ON-DEMAND switch between parallel and linear operation? So, if we have a 1000 cores, it switch to 10 with the linear power of 10 x 10? In my dreams this was very usefull, but wonder how feasible clould be ;)
- pcwalton 10y ago
  Sure: it's called a superscalar CPU.
- pjc50 10y ago
  No. Basically the limiting factor in most designs isn't so much arithmetic as fetches and branches. Especially cache misses. Theses are inherently linear operations - if you need to fetch from memory and then jump based on the result, for example. Superscalar 'cheats' somewhat by spending area to keep the pipeline fed, through branch prediction and suchlike. The nearest thing is the graphics card, which has a very large number of arithmetic units but less flow control, so you can run the same subroutine on lots of different data in parallel. Highly multicore chips make a different tradeoff: external memory bandwidth is very limited. Ideal for video codecs etc where you can take a small chunk and chew heavily. Very bad for running random unadapted C code, Java etc.
- wmf 10y ago
  There has been a bunch of academic research about this topic under names like core fusion and dynamic multicore. A recent sample: https://www.microsoft.com/en-us/research/wp-content/uploads/2016/02/2013-hpca-t3.pdf https://www.microsoft.com/en-us/research/wp-content/uploads/...
- flamedoge 10y ago
  yes. It's called FPGA.
- daurnimator 10y ago
  This is sort of what Hyperthreading is. Though you'll notice the ratios are not as good as what you want.

microcolonel 10y ago

Could be excellent for a dense automatic isolating array microphone; thousand other things. I'd love to see Parallella in embedded, they set a great example.

nickpsecurity 10y ago

I'm seeing NIDS for 10+Gbit links, DDOS mitigation, cache appliance for web servers, Erlang accelerator, BitTorrent accelerator, and so on. Quite a few possibilities. Also, something like this might be tuned for hardware synthesis, formal verification, or testing given all the resources that requires. Intel has a nice presentation showing what kind of computing resources go into their CPU work: https://www-ssl.intel.com/content/dam/www/public/us/en/documents/white-papers/intel-it-hpc-silicon-design-paper.pdf https://www-ssl.intel.com/content/dam/www/public/us/en/docum...

valarauca1 10y ago
I don't believe the chip has enough I/O for a 10Gb nic.
- adapteva 10y ago
  The issue is not bandwidth, it's the system cost. The chip has 1024 IO pins. (more than enough for MANY 10Gb nics...)
  - nickpsecurity 10y ago
    "The issue is not bandwidth, it's the system cost." What does that mean?

mamcx 10y ago

I have a naive question based in my dreams: Is possible to design a CPU that ON-DEMAND switch between parallel and linear operation? So, if we have a 1000 cores, it switch to 10 with the linear power of 10 x 10? In my dreams this was very usefull, but wonder how feasible clould be ;)

pcwalton 10y ago
Sure: it's called a superscalar CPU.
pjc50 10y ago
No. Basically the limiting factor in most designs isn't so much arithmetic as fetches and branches. Especially cache misses. Theses are inherently linear operations - if you need to fetch from memory and then jump based on the result, for example. Superscalar 'cheats' somewhat by spending area to keep the pipeline fed, through branch prediction and suchlike. The nearest thing is the graphics card, which has a very large number of arithmetic units but less flow control, so you can run the same subroutine on lots of different data in parallel. Highly multicore chips make a different tradeoff: external memory bandwidth is very limited. Ideal for video codecs etc where you can take a small chunk and chew heavily. Very bad for running random unadapted C code, Java etc.
wmf 10y ago
There has been a bunch of academic research about this topic under names like core fusion and dynamic multicore. A recent sample: https://www.microsoft.com/en-us/research/wp-content/uploads/2016/02/2013-hpca-t3.pdf https://www.microsoft.com/en-us/research/wp-content/uploads/...
flamedoge 10y ago
yes. It's called FPGA.
daurnimator 10y ago
This is sort of what Hyperthreading is. Though you'll notice the ratios are not as good as what you want.