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Did I read the specs wrong or are they claiming a 12x - 15x performance improvement over the Ivy Bridge Xeon in GFLOPS/watt? In a <2w package? http://www.adapt
by zelon88 10y ago
Did I read the specs wrong or are they claiming a 12x - 15x performance improvement over the Ivy Bridge Xeon in GFLOPS/watt? In a <2w package? http://www.adapteva.com/wp-content/uploads/2013/06/hpec12_olofsson_publish.pdf http://www.adapteva.com/wp-content/uploads/2013/06/hpec12_ol...
- dnautics 10y agoThat's not unreasonable.
- dnautics 10y agoI should clarify:. Presumably the parallella's RISC does away with a lot of the superscalar features of the x86 which are embedded in the xeon phi's One way to think about it is that things like branch prediction and speculative and out of order execution are like real-time JITting of your code. Not having that silicon can make things way more efficient.
- adapteva 10y agoThat's an older paper, but yes there have been more than one independent study showing 25x boost in terms of energy efficiency. See Ericsson FFT paper, OpenWall bcrypt paper, and others at parallella.org/publications.
- white-flame 10y agoThe Epiphany gains are certainly only achievable for massively pipelinable or embarrassingly parallel operations with very little intermediate state (e.g. streaming data, neural software, etc), not for random access large memory footprint crunching like the Xeon. There simply isn't the per-core memory (64KB), or external memory bandwidth, to go around otherwise. Xeon, Power, etc are kind of power pigs anyway, though they've got a lot of absolute oomph to show for it.