I was able to make successful projects with the Zynq a few years ago, but it is a pretty steep challenge - it requires pretty broad knowledge of software, Linux

I was able to make successful projects with the Zynq a few years ago, but it is a pretty steep challenge - it requires pretty broad knowledge of software, Linux, and hardware design. The general process was very convoluted - requiring HDL to be wrapped in top level components defined in the Vivado GUI. It worked well once you figured out what was going on, but the learning curve is pretty steep. I tried to touch the GUI as least as possible - I did unit tests with Icarus Verilog instead, and had my own script for packaging and live reloading the FPGA bitstream (a pretty neat trick that Xilinx pulls off, there). I did wonder how someone lacking any of the pieces of knowledge would ever get it to work - and indeed, a blog post I made about it working gathered many responses of people having trouble making a similar basic project. A side note - the Zynq is one of the better documented SoCs out there (aside from the FPGA bitstream itself), so it might be worth considering just for that. I also have tried Clifford Wolf's tools, and they are absolutely wonderful. It's the way I wish all FPGAs worked. It's amazingly complete - I wouldn't hesitate to ship a product using a bitstream generated from yosys/arachne/icestorm. Extra extra side note - in some cases that used to require FPGAs, you can now get away with bit-banging from a normal microcontroller. Most newish micros can do single cycle GPIO writes, and can be clocked over 100MHz.