4 ms·

Didn't know about this. They should have gone with AMD.

by teaearlgraycold 10y ago

mordocai 10y ago
https://libreboot.org/faq/#amd https://libreboot.org/faq/#amd. ARM maybe?
- Cyph0n 10y ago
  ARM has TrustZone.
  - monocasa 10y ago
    TrustZone is, for practical purposes, a little more open if you're the one designing the board. Most of the time, the crypto is opt in, and you as the final assembler control the keys.
  - subway 10y ago
    TrustZone alone is much closer to a SecureBoot or TPMish feature than ME. It's possible it would allow implementation of an ME-like software stack running inside the TEE. It's worth mentioning that there is at least one OSS implementation of a TEE software stack, OP-TEE, making this even less of an issue. Assuming your device/soc mfg doesn't lock you out. http://www.linaro.org/blog/core-dump/op-tee-open-source-security-mass-market/ http://www.linaro.org/blog/core-dump/op-tee-open-source-secu...
calcifer 10y ago
AMD has it too: https://libreboot.org/faq/#amdpsp https://libreboot.org/faq/#amdpsp
DashRattlesnake 10y ago
If you want to get away from that kind of thing, right now I think you're options are POWER8: https://www.raptorengineering.com/TALOS/prerelease.php https://www.raptorengineering.com/TALOS/prerelease.php AMD has something similar to the Intel Management Engine: https://libreboot.org/faq/#amd https://libreboot.org/faq/#amd
- dorfsmay 10y ago
  Not SPARC?
  - nickpsecurity 10y ago
    Specifically, the OpenSPARC T2: http://www.oracle.com/technetwork/systems/opensparc/opensparc-t2-page-1446157.html http://www.oracle.com/technetwork/systems/opensparc/openspar... The ASIC implementation was nice: https://en.wikipedia.org/wiki/UltraSPARC_T2 https://en.wikipedia.org/wiki/UltraSPARC_T2 On a 65nm node... very outdated one... it might get 8 threads in 8 cores at 1.6GHz each with hardware RNG, crypto accelerators, and hypervisor support. That's the kind of implementation that would be useless for an open-source, secure workstation, server, or HPC node. ;) Especially if one slightly increased single-core performance or cache when porting it to 45nm. Forget that, though. Let's see what IBM will charge for their admittedly-faster pile of complicated silicon that only certain people can see which they've already turned into non-backdoored chips for you. ;)
    - apaprocki 10y ago
      Sadly the T1/T2 are ancient now. The non-open SPARC is up to T7, which is 20nm process, 256 threads on 32 cores.
      - nickpsecurity 10y ago
        Sort of. I run the bloated Web, movies, IDE's, servers, and VM's on a Core Duo with 2 cores under 2GHz done on 65nm. I'd loose some single-threaded performance probably with an OpenSPARC T2 but otherwise it should handle my modern workload. Doesn't quite feel ancient. ;) The cool thing about open-source CPU's is one can always improve on them to, say, have an extra dozen cores on more recent nodes. Like Oracle does but probably less impressive with less money.
        apaprocki 10y ago
        As a 2011 MBA user, I totally understand sticking with old tech that works. T1/T2 isn't really apples-to-apples, though. I came across this random quote from the libgmp devs that made me laugh: "SPARC chips before T4 under-perform on GMP. This is not because the GMP code is inadequately optimised for SPARC, but due to the basic v9 ISA as well as the micro-architecture of these chips. The T1 and T2 chips perform worse than any other SPARC chips; they compare to a 15 year older 486 chip." ouch!
hackermailman 10y ago
My Rockchip Chromebook doesn't have proprietary microcode, libreboot supported, costs $200. Only proprietary issue is the 3D acceleration
- Johan-bjareholt 10y ago
  That is the case with many ARM processors. There is a lot of work being made on iGPUs on ARM processors aswell currently such as freedreno, will hopefully be possible to have a good fully open source experience in a few years with arm linux computers.

Didn't know about this. They should have gone with AMD.

mordocai 10y ago

https://libreboot.org/faq/#amd https://libreboot.org/faq/#amd. ARM maybe?

Cyph0n 10y ago
ARM has TrustZone.
- monocasa 10y ago
  TrustZone is, for practical purposes, a little more open if you're the one designing the board. Most of the time, the crypto is opt in, and you as the final assembler control the keys.
- subway 10y ago
  TrustZone alone is much closer to a SecureBoot or TPMish feature than ME. It's possible it would allow implementation of an ME-like software stack running inside the TEE. It's worth mentioning that there is at least one OSS implementation of a TEE software stack, OP-TEE, making this even less of an issue. Assuming your device/soc mfg doesn't lock you out. http://www.linaro.org/blog/core-dump/op-tee-open-source-security-mass-market/ http://www.linaro.org/blog/core-dump/op-tee-open-source-secu...

calcifer 10y ago

AMD has it too: https://libreboot.org/faq/#amdpsp https://libreboot.org/faq/#amdpsp

DashRattlesnake 10y ago

If you want to get away from that kind of thing, right now I think you're options are POWER8: https://www.raptorengineering.com/TALOS/prerelease.php https://www.raptorengineering.com/TALOS/prerelease.php AMD has something similar to the Intel Management Engine: https://libreboot.org/faq/#amd https://libreboot.org/faq/#amd

dorfsmay 10y ago
Not SPARC?
- nickpsecurity 10y ago
  Specifically, the OpenSPARC T2: http://www.oracle.com/technetwork/systems/opensparc/opensparc-t2-page-1446157.html http://www.oracle.com/technetwork/systems/opensparc/openspar... The ASIC implementation was nice: https://en.wikipedia.org/wiki/UltraSPARC_T2 https://en.wikipedia.org/wiki/UltraSPARC_T2 On a 65nm node... very outdated one... it might get 8 threads in 8 cores at 1.6GHz each with hardware RNG, crypto accelerators, and hypervisor support. That's the kind of implementation that would be useless for an open-source, secure workstation, server, or HPC node. ;) Especially if one slightly increased single-core performance or cache when porting it to 45nm. Forget that, though. Let's see what IBM will charge for their admittedly-faster pile of complicated silicon that only certain people can see which they've already turned into non-backdoored chips for you. ;)
  - apaprocki 10y ago
    Sadly the T1/T2 are ancient now. The non-open SPARC is up to T7, which is 20nm process, 256 threads on 32 cores.
    - nickpsecurity 10y ago
      Sort of. I run the bloated Web, movies, IDE's, servers, and VM's on a Core Duo with 2 cores under 2GHz done on 65nm. I'd loose some single-threaded performance probably with an OpenSPARC T2 but otherwise it should handle my modern workload. Doesn't quite feel ancient. ;) The cool thing about open-source CPU's is one can always improve on them to, say, have an extra dozen cores on more recent nodes. Like Oracle does but probably less impressive with less money.
      - apaprocki 10y ago
        As a 2011 MBA user, I totally understand sticking with old tech that works. T1/T2 isn't really apples-to-apples, though. I came across this random quote from the libgmp devs that made me laugh: "SPARC chips before T4 under-perform on GMP. This is not because the GMP code is inadequately optimised for SPARC, but due to the basic v9 ISA as well as the micro-architecture of these chips. The T1 and T2 chips perform worse than any other SPARC chips; they compare to a 15 year older 486 chip." ouch!

hackermailman 10y ago

My Rockchip Chromebook doesn't have proprietary microcode, libreboot supported, costs $200. Only proprietary issue is the 3D acceleration

Johan-bjareholt 10y ago
That is the case with many ARM processors. There is a lot of work being made on iGPUs on ARM processors aswell currently such as freedreno, will hopefully be possible to have a good fully open source experience in a few years with arm linux computers.