They already take some care with RISC-V to avoid introducing instructions they will likely need to a) supersede or b) deprecate in the future. A good example is

They already take some care with RISC-V to avoid introducing instructions they will likely need to a) supersede or b) deprecate in the future. A good example is the approach they are taking to vectors. Instead of adding a SIMD extension which will need widening or new infrastructure every few months; they are going to introduce a hardware pipelined vector extension which can work on vector units of any width.