I think one of the things that is incorrect in this article is the software used to design asics (Custom Chips). Synopsys, Cadence, Mentor, Magma (when it was a

I think one of the things that is incorrect in this article is the software used to design asics (Custom Chips). Synopsys, Cadence, Mentor, Magma (when it was around) all made pretty good tools. The thing is the weren't free. Also you had to use TCL, but they could take rtl (Verilog aka the design language) to GDS (what gets fabbed). Heck there always seemed to be some startup that claimed they came up with a better routing tool or a better timing tool. They weren't super complicated to use. If you had too many gates you had to script a bunch of hacks, but it isn't too hard.