3 ms·
The hardware internally doesn't use tristate signals, but your VHDL compiler should be smart enough to turn... pin <= 'Z' WHEN tristate ELSE '0' WHEN zero
by cnvogel 10y ago
The hardware internally doesn't use tristate signals, but your VHDL compiler should be smart enough to turn...
pin <= 'Z' WHEN tristate ELSE '0' WHEN zero ELSE '1';
...into an instantiation of a tristate IO-buffer on an external "pin" which can high-Z. Sometimes the logic isn't that trivial, though, and you (as a programmer) might not realize that your code actually prohibits the pin from going 'Z'... (or you've confused the VHDL compiler).
Better stick to something explicitly simple as the code above, or directly instantiate a bidirectional I/O pin from your chip vendor's VHDL library:
the_pin: IOBUF port map (
T => tristate, -- '1' == high_z
I => data_out, -- data leaving the FPGA, may be tristated
O => data_in, -- data entering the FPGA
IO => pin); -- physical I/O pin
- DigitalJack 10y agoI wouldn't recommend letting a tool decide what your IO is supposed to be.
- cnvogel 10y agoThere are cases where you absolutely must instantiate something from your vendor's libraries. But inference tristate I/O from a single concurrent statement will be safe (and also the recommended way to handle tristate i/o on the three platforms I've used). -- output data, driven active when \WR is LOW, high-Z otherwise d <= d_out WHEN wr_en_n = '0' ELSE (others => 'Z'); -- input data d_in <= d; Just don't bury the logic in some deeply nested if/else tree tree in a process or state machine, this is likely to not synthetize to what you had intended. :-).