My understanding of the problem is that Digilent's reference FPGA implementation for RAM access uses tristate signals, so it only works in specific configuratio

My understanding of the problem is that Digilent's reference FPGA implementation for RAM access uses tristate signals, so it only works in specific configurations. Carl's blog has details: https://rescue1130.blogspot.com/2016/09/ram-problems-due-to-xilinx-handling-of.html https://rescue1130.blogspot.com/2016/09/ram-problems-due-to-...