>An astute reader might realize that computing the cache line on every invocation is not enough for user space code: It can happen that a process gets scheduled

>An astute reader might realize that computing the cache line on every invocation is not enough for user space code: It can happen that a process gets scheduled on a different CPU while executing the __clear_cache function with a certain cache line size, where it might not be valid anymore. Doesn't ARM have an "Enter Critical Region" instruction?