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You could also say that the ARM implementation is not optimal since it uses the same cache size for vastly different designs (different pipeline length and memo
by pawadu 10y ago
You could also say that the ARM implementation is not optimal since it uses the same cache size for vastly different designs (different pipeline length and memory access characteristics).
Samsung tried to improve performance, I don't think they are at fault at all.
- gcp 10y agoSamsung's design breaks correctly written user-land code. Hence, they're 100% at fault. Going to 128-byte cache lines was fine, but they should have made the lower-power part of the chip match (which in this case they likely couldn't because they licensed that design), or they should have made sure 128-byte lines were reported in all circumstances (which requires a hack similar to the workaround done in the kernel because again they can't make the A53 report 64 bytes).
- sangnoir 10y ago> Samsung's design breaks correctly written user-land code. Hence, they're 100% at fault. This is similar to blaming OS/BIOS manufaturers for Y2K breaking "correctly written code" at the turn of the millenium.The code was incorrect in this instance because it assumed the cache size would be the same for all cores, Samsung simply manufactured a SOC that breaks that faulty assumption.
- gcp 10y agoThe assumption isn't faulty, it's guaranteed to be right. And it has to be, or there's no way to write functional code for ARM.
- abysmallyideal 10y agoThat is a bit far-fetched, as it seems to mostly affect how mono and gcc(?) JIT is designed.
- oshepherd 10y agoThe architecture states that CTR_EL0 reports the _minimum_ ICache line size across all cores. In this system, that would be 64 bytes.
- pawadu 10y agoCan you point me to the manual that does say so? This is all I could find on the subject > [3:0] IminLine Log 2 of the number of words in the smallest cache line of all the Instruction Caches that the processor controls. > This values is: > 0x4 > Smallest Instruction Cache line size is 16 words.
- pawadu 10y ago> Samsung's design breaks correctly written user-land code. Are you sure? From the article, it sounds to me that the real cause of the error is an incorrect assumption made by the GCC people.
- gcp 10y agoYes, I am sure. If we forget about the ARM spec explicitly enforcing this anyway, here's some food for thought: how exactly do you suppose the GCC people could write correct code, if they aren't allowed to make that assumption?
- pawadu 10y agoOkay, I did not know that. But could you point me to the part of the spec that says this? I wasn't able to find this in their public specs.
- gcp 10y agoARM ARM, section B2.2.6 The CTR holds minimum line length values for: - the instruction caches ...this value is the most efficient address stride to use to apply to a sequence of address-based maintenance operations to a range of addresses... The documentation for the CTR_EL0 reg talks about "caches under this processors control" which you could argue don't include other cores, but if you allow migration between cores, then line size changes underneath running software break the above "most efficient address stride" assumption. So you can't do that. It boils down to this: If you can't assume that cache line size doesn't change underneath you, then you can't invalidate line by line at all, and would have to go word by word. That's terrible for performance (and a huge waste), which is why the spec says to use the above value for those operations.
- pawadu 10y agoI appreciate you digging up the relevant text from the manual, but I don't think you should accuse Samsung of wrongdoing based on such far fetched assumptions. That document does not explicitly forbids this. In addition, take a look at their sample code which indeed reads some cache configuration registers during each call. The same code is found verbatim in the linux kernel, if you now don't trust the ARM engineers :)