3 ms·
Why not proactively check all the chips to make sure all gates are working on each chip, rather than try to debug when something breaks?
by source99 10y ago
Why not proactively check all the chips to make sure all gates are working on each chip, rather than try to debug when something breaks?
- kens 10y agoChecking all the chips would be very, very time consuming. Not to mention we'd need to build some sort of test setup for each chip. It's more likely we'd cause a problem (e.g. bend a pin) than fix a problem.
- source99 10y agoBut wouldn't it be fun to build a raspberry pi based chip tester!
- cnvogel 10y agoAll the contemporary CPUs you find on affordable boards have only 3.3V (maybe some even 1.8V, at least on a subset of pounds) I/O. Not directly connect able to chips as used in the Alto. There are still a few CPLD/FPGA available with 5V capable banks, which would be preferable, so you'd build a JTAG TAP for single ICs. At this point, you could as well connect it to a PC using a JTAG pod .
- avian 10y agoWe used to have an old EPROM (the UV-erasable kind) programmer in the lab. I remember it also had a mode for testing 74xx series logic. I don't think it was ever used in that capacity though.
- makomk 10y agoI actually watched a YouTube video the other day where someone used a similar programmer to test all the logic chips in his ZX-80: https://youtu.be/qqUxXrh_xgM https://youtu.be/qqUxXrh_xgM (Spoiler warning: it didn't find the failure.)