It looks like you can read and write data via the instruction bus --- which you'd have to, as e.g. SRAM0 is only available on the instruction bus. It claims to

It looks like you can read and write data via the instruction bus --- which you'd have to, as e.g. SRAM0 is only available on the instruction bus. It claims to be Harvard architecture, but both buses access the same memory, so it's really von Neumann architecture. So I'm not really sure what the difference is. Is it just that they took a Harvard architecture processor core and mostly wired both buses to the same memory? (And as you say, the reversed mapping of SRAM1 is just weird.) Also, if I read this correctly, you can use a non-addressable storage device (like SPI flash) and it'll demand load it via a cache? That's amazing. In short: I really like it. Sensible processors are so dull.