4 ms·
That manual looks great, and probably should have been linked from the Hackaday post. I'm confused by this, on page 12: > The capacity of Internal SRAM 1 is 1
by teraflop 10y ago
That manual looks great, and probably should have been linked from the Hackaday post.
I'm confused by this, on page 12:
> The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses 0x3FFE_0000 ~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the instruction bus. The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via the data bus.
That word-reversed mapping seems like a slightly nutty design quirk, but I find it hard to imagine how it could happen by accident. If it's a deliberate feature, is there anything it would actually be useful for?
- PinguTS 10y agoThis seems to be very odd. May be someone wanted to make access easy and fucked it up. Then they left it and defined it as feature. The original feature is may be, that data access is byte wise, but as it is 32-bit CPU the instruction access is double-word wise. As it is also little endian someone may wanted to make the access easy.
- pjc50 10y agoIt's weirder than that: within a word the bytes are in order, it appears that "top" and "bottom" of memory have been exchanged. It's as if one address bus is being fed through an inverter.
- deleted 10y ago[deleted]
- david-given 10y agoI don't think it's an inverter. It looks like a subtraction (which is even weirder). Here's the example they give: 0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC. 0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8. 0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8. 0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8. 0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8. …… 0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004. 0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000. 0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000.
- teraflop 10y agoYeah, I've seen similar tricks on ARM microcontrollers that have 32-bit address spaces and tiny amounts of memory. e.g. https://spin.atomicobject.com/2013/02/08/bit-banding/ https://spin.atomicobject.com/2013/02/08/bit-banding/ But the reverse ordering has me scratching my head. I guess you could use it to support rudimentary multi-threading, with two different stacks growing in opposite directions...
- andy_ppp 10y agoJust a wild guess but is it so that each CPU can have it's own stack/allocate memory from each end without conflict until they meet?
- david-given 10y agoIt looks like you can read and write data via the instruction bus --- which you'd have to, as e.g. SRAM0 is only available on the instruction bus. It claims to be Harvard architecture, but both buses access the same memory, so it's really von Neumann architecture. So I'm not really sure what the difference is. Is it just that they took a Harvard architecture processor core and mostly wired both buses to the same memory? (And as you say, the reversed mapping of SRAM1 is just weird.) Also, if I read this correctly, you can use a non-addressable storage device (like SPI flash) and it'll demand load it via a cache? That's amazing. In short: I really like it. Sensible processors are so dull.
- cnvogel 10y ago> you can use a non-addressable storage device (like SPI flash) and it'll demand load it via a cache? That's amazing. This is already done like this on the esp8266.
- ChuckMcM 10y agoOne wonders if this is a poorly translated explanation for a little-endian architecture. When accessed as data it comes back big-endian but when accessed as instructions it is interpreted as little-endian? I could imagine a hack like this where the CPU logic came from one vendor that had the opposite byte order than a previous CPU, and yet one wanted to keep some level of compatibility between them.