The article a little out of date. The RISC vs CISC distinction is very blurry these days. Most RISC architectures have been made more CISCy, and vice versa. T

The article a little out of date. The RISC vs CISC distinction is very blurry these days. Most RISC architectures have been made more CISCy, and vice versa. The article mentions CISC CPUs using RISC instructions internally, which isn't the whole story anymore. Ars Technica did a classic article on this debate (in 1999!): http://arstechnica.com/cpu/4q99/risc-cisc/rvc-1.html http://arstechnica.com/cpu/4q99/risc-cisc/rvc-1.html and a follow up here: http://arstechnica.com/hardware/news/2009/09/retrospect-and-prospect-ten-years-of-risc-vs-cisc.ars/ http://arstechnica.com/hardware/news/2009/09/retrospect-and-... A particularly interesting part of the follow up: "But a funny thing happened with the Pentium M: processor designers discovered that processors of all types are actually more power-efficient if their internal instruction format is more complex, compound, and varied than it is with simple, atomic RISC operations ... ... The end result is that even RISC processors needed to get more CISC-y on the inside if they wanted to juggle the largest number of in-flight instructions using the least amount of power."