I think one thing that ought to be dealt with first before any RISC-CISC debate is what exactly defines either one. Some attributes commonly identified (in my

I think one thing that ought to be dealt with first before any RISC-CISC debate is what exactly defines either one. Some attributes commonly identified (in my experience) with RISC machines include: - Fixed-width instructions (generally 32 bits) - Explicit load and store instructions with arithmetic being performed only between registers (hence RISC architectures sometimes being called load-store) - Large register files with few or no special-purpose registers (MIPS HI/LO registers being an exception to this one, for example) Other common (though perhaps less "defining") traits: three-operand instructions, relatively few/simple addressing modes, procedure calls often done via "branch-and-link" instructions, etc. But... > A RISC processor is a processor with no microcode virtual machine level. Huh? I've certainly never heard that before. In fact, I'd say the RISC/CISC dichotomy is primarily (if not entirely) an attribute of the ISA, not the microarchitecture implementing it. It's generally pretty easy to look at e.g. a PPC or x86 instruction set and classify it one way or another; in terms of internal implementations though, the lines have gotten so blurred (in both directions) in modern machines that I don't think it's real meaningful to talk about RISC vs CISC anymore at the microarchitectural level, frankly.