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Article: In fact, it’s now a universally accepted truth that RISC is better than CISC! Actually, because of how much more efficient RISC machines a

Article: In fact, it’s now a universally accepted truth that RISC is better than CISC! Actually, because of how much more efficient RISC machines are than their CISC counterparts, most CISC CPUs convert their CISC instructions into RISC instructions internally, then run them! Most RISC CPUs convert their RISC instructions into RISC internally, then run them! Look at the G5 (IBM PowerPC 970): it does register renaming, and divides and assembles its instructions for the purpose of out-of-order execution, just like any out-of-order CISC processor. The truth is that instruction sets are always outdated compared to the number of transistors that Moore's law allow to put on a chip. At some time it seemed that 32 registers would make renaming unnecessary. At another it seemed VLIW would make possible a level of performance not allowed by older instruction sets. Ask Intel and HP how that transition worked out for them. RISC principles are only superior in the sense that 70's crazy haircuts are superior to 60's crazy haircuts. They are dated too, just a little less so. And in these days of memory-bound computations, higher density in CISC instruction sets seems to give them a slight advantage, if anything.

derefr 17y ago
> Most RISC CPUs convert their RISC instructions into RISC internally, then run them! A RISC processor is a processor with no microcode virtual machine level. These processors aren't RISC in anyone's view but marketing's. Likely, there are very few true RISC processors still being designed (for speed; processors for embedding are a different story.)
- 1amzave 17y ago
  I think one thing that ought to be dealt with first before any RISC-CISC debate is what exactly defines either one. Some attributes commonly identified (in my experience) with RISC machines include: - Fixed-width instructions (generally 32 bits) - Explicit load and store instructions with arithmetic being performed only between registers (hence RISC architectures sometimes being called load-store) - Large register files with few or no special-purpose registers (MIPS HI/LO registers being an exception to this one, for example) Other common (though perhaps less "defining") traits: three-operand instructions, relatively few/simple addressing modes, procedure calls often done via "branch-and-link" instructions, etc. But... > A RISC processor is a processor with no microcode virtual machine level. Huh? I've certainly never heard that before. In fact, I'd say the RISC/CISC dichotomy is primarily (if not entirely) an attribute of the ISA, not the microarchitecture implementing it. It's generally pretty easy to look at e.g. a PPC or x86 instruction set and classify it one way or another; in terms of internal implementations though, the lines have gotten so blurred (in both directions) in modern machines that I don't think it's real meaningful to talk about RISC vs CISC anymore at the microarchitectural level, frankly.
  - derefr 17y ago
    > I've certainly never heard that before. It's because we've adopted (or rather, co-opted) the terms to refer to things that shared phenotypical traits with their progenitors, but no longer held true to the original definitions. In reality, RISC originally just meant "exposes its microarchitecture as its instruction-set architecture." All the other well-known properties of RISC machines were effects of this decision. But these days, > the lines have gotten so blurred (in both directions) in modern machines ...that, like I said, there are very few RISC processors under the original, theoretical definition of the term (and it's probably alright to just use "RISC" under the new definition, since only the embedded programmers will complain.)

derefr 17y ago

> Most RISC CPUs convert their RISC instructions into RISC internally, then run them! A RISC processor is a processor with no microcode virtual machine level. These processors aren't RISC in anyone's view but marketing's. Likely, there are very few true RISC processors still being designed (for speed; processors for embedding are a different story.)

1amzave 17y ago
I think one thing that ought to be dealt with first before any RISC-CISC debate is what exactly defines either one. Some attributes commonly identified (in my experience) with RISC machines include: - Fixed-width instructions (generally 32 bits) - Explicit load and store instructions with arithmetic being performed only between registers (hence RISC architectures sometimes being called load-store) - Large register files with few or no special-purpose registers (MIPS HI/LO registers being an exception to this one, for example) Other common (though perhaps less "defining") traits: three-operand instructions, relatively few/simple addressing modes, procedure calls often done via "branch-and-link" instructions, etc. But... > A RISC processor is a processor with no microcode virtual machine level. Huh? I've certainly never heard that before. In fact, I'd say the RISC/CISC dichotomy is primarily (if not entirely) an attribute of the ISA, not the microarchitecture implementing it. It's generally pretty easy to look at e.g. a PPC or x86 instruction set and classify it one way or another; in terms of internal implementations though, the lines have gotten so blurred (in both directions) in modern machines that I don't think it's real meaningful to talk about RISC vs CISC anymore at the microarchitectural level, frankly.
- derefr 17y ago
  > I've certainly never heard that before. It's because we've adopted (or rather, co-opted) the terms to refer to things that shared phenotypical traits with their progenitors, but no longer held true to the original definitions. In reality, RISC originally just meant "exposes its microarchitecture as its instruction-set architecture." All the other well-known properties of RISC machines were effects of this decision. But these days, > the lines have gotten so blurred (in both directions) in modern machines ...that, like I said, there are very few RISC processors under the original, theoretical definition of the term (and it's probably alright to just use "RISC" under the new definition, since only the embedded programmers will complain.)