> To me though, nothing says it clearer than that Intel internally converts CISC instructions to a series of RISC instructions, then enters them into the pipeli

> To me though, nothing says it clearer than that Intel internally converts CISC instructions to a series of RISC instructions, then enters them into the pipeline. One problem with that argument is that RISC machines do the same thing. Another problem is that there are different amounts of available/potential bandwidth at different points. For example, L2 accesses are far more expensive than what a decoder can produce. There's always some benefit to reducing the number of control bits, but it is especially pronounced the further that you get from functional units. BTW - "the pipeline" is misleading. Many implementations use multiple pipelines even for a single instruction stream. > Within the field though, it's taken for fact. There may be a theoretical advantage, but if so, it is small relative to many other factors. I've actually helped define a commercial ISA (RISC FWIW).